A need frequently arises to upscale video images while displaying these video images on computer systems. For example, a CD-ROM decoder in a computer system may generate a source video image of size 160.times.120 pixels and the image may need to be displayed on a display area of size 640.times.480 pixels on a display screen of the computer system. In such a situation where the size of the display image is larger than the size of the source image, the source video image needs to be upscaled to the larger display image while still maintaining the characteristics of the source video image.
Interpolation is a well-known prior art technique used for upscaling video images. In an interpolation scheme, several adjacent pixels in a source video image are typically used to generate additional new pixels. FIG. 1 shows pixels (A, B, C, and D) of the source video image and pixels (E-P) that are additionally generated by interpolation to upscale the source video image. Pixel E may be generated, for example, by formula (2/3 A+1/3 B). If each of the pixels is represented in RGB format, RGB components of pixel E may be generated by using corresponding components of pixels A, B. Pixel K may similarly be generated using the formula (1/3 A+2/3 C). The generation of pixels such as E, F may be termed horizontal interpolation as pixels E, F are generated using pixels A, B located horizontally. Generation of pixels such as G, K may be termed vertical interpolation.
Graphic controller chips in prior art computer systems may use a display memory to store source image data prior to upscaling the source image. Such graphics controller chips may store the pixels in a scan line dominant order, i.e. pixels corresponding to a given scan line may be stored in consecutive locations in display memory prior to storing pixels of a subsequent scan line. Such a scan line dominant order of storing may cause pixels of different scan lines to be stored in different pages of display memory.
During vertical interpolation of source image data, throughput performance problems may be encountered in a scan line dominant order of storing scheme because vertical interpolation usually requires pixels from different scan lines. Accessing different scan lines may require retrieving data from different pages of the display memory forcing a non-aligned or non-page mode read access. A non-page mode read access may require more clock cycles than a page mode access for memory locations within a pre-charged row. Thus the average memory access time during vertical interpolation may be much higher than consecutive memory accesses within the same row. High average memory access time during vertical interpolation may result in a decrease in the overall throughput performance of a graphics controller chip.
To minimize number of accesses across different rows, a graphics controller chip may retrieve and store a previous scan line in a local memory element. For example, with respect to FIG. 1, a graphics controller chip may retrieve and store all pixels corresponding to scan line A-B and store retrieved pixels in a local memory located in the graphics controller chip. The graphics controller chip may then retrieve pixels corresponding to scan line C-D, and interpolate using pixels stored in the local memory.
One problem with such a scheme employing local memory is that a large local memory may be required. For example, to store 720 pixels of a scan line with each pixel being represented in RGB format, and with each of RGB components stored as eight bits, a memory of size 720.times.3.times.8=17280 bits may be required. Such a large local memory may increase the cost of graphics controller chips besides requiring additional silicon space.
More over, interpolation schemes which make use of multiple scan lines may require a correspondingly bigger local memory. For example, a more sophisticated interpolation scheme may use more than two scan lines to generate additional pixels for upscaling.